Split gate cells for embedded flash memory

ABSTRACT

In a method of forming a split gate memory cell, a sacrificial spacer is formed over a semiconductor substrate. A first layer of conductive material is formed over a top surface and sidewalls of the sacrificial spacer. A first etch back process is formed on the first layer of conductive material to expose the top surface of the sacrificial spacer and upper sidewall regions of the sacrificial spacer. A conformal silicide-blocking layer is then formed which extends over the etched back first layer of conductive material and over the top surface of the sacrificial spacer.

REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part application which claimspriority to U.S. application Ser. No. 14/182,952 filed on Feb. 18, 2014and entitled, “SPLIT GATE MEMORY DEVICE AND METHOD OF FABRICATING THESAME”; the contents of which are incorporated herewith in theirentirety.

BACKGROUND

Flash memory is an electronic non-volatile computer storage medium thatcan be electrically erased and reprogrammed. Flash cells are used in awide variety of commercial and military electronic devices andequipment. In flash memory cells, over erase associated with stackedgate structures is eliminated by the use of a split gate structure.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 shows a cross-sectional view of a pair of adjacent memory cellsaccording to some embodiments of the present disclosure.

FIG. 2 shows a flow diagram of a method according to some embodiments ofthe present disclosure.

FIG. 3 shows a flow diagram of a method for forming split gate memorydevice according to some embodiments of the present disclosure.

FIGS. 4-17 show cross-sectional views at various stages of forming asplit gate memory cell according to some embodiments of the presentdisclosure.

FIG. 18 shows a cross-sectional view of a pair of adjacent flash memorycells according to some embodiments of the present disclosure.

FIG. 19 shows a flow diagram of a method for forming a pair ofself-aligned split gate flash memory cells according to some embodimentsof the present disclosure.

FIGS. 20-34 show a series of cross-sectional views at various stages offorming a split gate memory cell according to some embodiments of thepresent disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Split gate memory cells have promising advantages over stacked gatememory cells such as low power consumption, high injection efficiency,less susceptibility to short channel effects, and over erase immunity.The built in select gate transistor in a split gate memory cell caneffectively get rid of the on-chip erase procedures that were used intraditional stacked gate cells to resolve over erase problems.Traditional fabrication methods of the split gate memory cells involvemany processing steps which include patterned masking and dry etchingsteps. The large number of processing steps results in substantialfabrication costs.

The conventional process for fabricating flash memory usually usesphotomasks to define the devices. Since the precision of the photomasksis limited, misalignment can occur for features with dimensions whichare less than some minimal line width design rule or which are spacedmore closely than some minimal spacing design rule. This misalignment,if any, can lead to gaps between elements intended to be coupledtogether (e.g., undesired open circuits) and/or can lead to bridgingbetween elements intended to be isolated (e.g., undesired shortcircuits), either of which can cause the flash memory device to fail.Therefore, density for conventional flash memory devices has beenlimited by these design rules. To pack these conventional flash cellscloser together, self-aligned select gates (SG) and memory gates (MG)are used. These self-aligned structures form a pair of flash gates—socalled “split gates”—on opposite sides of a sacrificial spacer. Thisprocess enables formation of symmetric structures with smaller criticaldimensions and, hence, denser data storage.

In order to lower manufacturing cost, simplify the manufacturingprocedures, and increase operational speed for a semiconductor device, atrend in semiconductor manufacturing is to integrate different devices,such as a memory cell and a logic circuit, on the same wafer. An exampleof this is modern embedded flash memory devices. These embedded flashmemory devices include an array of flash memory cells and peripherycircuitry formed on the same wafer. High-k metal gate (HKMG) technologyhas become one of the front-runners for the next generation of CMOSdevices, and this technology incorporates a high-k dielectric, whichreduces leakage and improves the dielectric constant. To help withfermi-level pinning and to allow the gate to be adjusted to lowthreshold voltages, a metal gate is used instead of a polysilicon gate.By combining the metal gate and low-k dielectric, HKMG technologyreduces gate leakage, thereby increasing the transistor capacitance andallowing chips to function with reduced power needs. HKMG processtechnology involves two distinctly different integration flows, namelytraditional gate and replacement gate. In a traditional gate approach,the transistor's gate stack is fabricated first, followed by the sourceand drain, very much like traditional CMOS transistor architecture. Areplacement gate process is just the opposite, where a sacrificial gatestack is stripped away to form a recess after source and drain regionshave been formed, and a replacement gate is fabricated in the recessafter formation of the source and drain regions.

Flash memory formed by conventional methods can only be embedded intraditional gate HKMG technology and is not compatible with replacementHKMG technology. The reason for this incompatibility stems from achemical mechanical polishing (CMP) process used in the replacement gateprocess. This CMP process is performed immediately before thepolysilicon gates are removed, and planarizes the structure until thetop surface of the polysilicon gates are reached. In self aligned flashmemory cells, usually a self-aligned silicide or salicide is formed onthe base of the semiconductor surface in the active regions to provideelectrical connection. This layer of salicide (self-aligned silicide) isalso formed on top surfaces of the select gates (SGs) and the memorygates (MGs) during salicide formation on the base of the semiconductorsurface. If self-aligned split-gate flash memory cells with salicide ontop of the gate structures are embedded in the replacement gate processof a HKMG integrated circuit, the above mentioned CMP process willdamage the SGs of the memory cells due to metal ions from the silicidecontaminating other areas of the wafer/IC as CMP occurs. Ultimately,this contamination can reduce manufacturing yields and render some ICsunusable or less than optimal.

Accordingly, the present disclosure relates to a new processing methodwhich makes it practical to integrate embedded flash memory in areplacement gate HKMG circuit by protecting the top surfaces of SGsbefore salicide formation. In particular, in some embodiments, asilicide-blocking material is formed over the top surfaces of the SGs.This silicide-blocking material prevents silicide formation on the topsurfaces of the SGs during silicide formation on the active regions.Therefore, when CMP is carried out, the top surfaces of the SGs (nowlacking a salicide/silicide thereon) are still subject to a CMPoperation to planarize the SG top surfaces with other features on aperiphery of the chip. However, because the top surfaces of the SG nolonger include the salicide/silicide, the CMP operation will not causecontamination for the periphery of the chip as in conventionalapproaches. Therefore, the resultant embedded flash memory andsurrounding CMOS peripheral circuitry can be manufactured with higheryield and better reliability than previous approaches.

FIG. 18 shows a cross-sectional view of a semiconductor body thatincludes a pair of split gate flash memory cells 1800 in accordance withsome embodiments. The pair of split gate flash memory cells 1800includes a first memory cell 1802 a and a second memory cell 1802 b thatresides over a semiconductor substrate 1801. The first and second memorycells 1802 a, 1802 b each include a memory cell gate structure that isarranged over a channel region separating source/drain regions of thememory cell. Thus, the first memory cell 1802 a includes a first memorygate structure 1804 a arranged between a first source/drain region 1806a and a second source/drain region 1806 b; and the second memory cell1802 b includes a second memory gate structure 1804 b arranged betweenthe second source/drain region 1806 b and a third source/drain region1806 c. The second source/drain region 1806 b thus acts as a shared orcommon source/drain (S/D) region for the first and second memory cells1802 a, 1802 b. Conductive contacts 1808, which can be made of Ti/TiN(titanium/titanium nitride) and/or W (tungsten) in some embodiments,extend downwardly to contact to silicide regions 1810 on upper regionsof the source/drain regions 1806.

The memory gate structures 1804 are made of several sub-structures,including select gates, memory gates, and charge trapping layers, andhave a memory gate lower surface that is separated from an upper surfaceof the semiconductor substrate by a base oxide 1812. More particularly,the first memory cell gate structure 1804 a comprises a first selectgate (SG) 1814 a and a first memory gate (MG) 1816 a; and the secondmemory cell gate structure 1804 b comprises a second SG 1814 b and asecond MG 1816 b. In some embodiments, the first and second SGs 1814 a,1814 b and the first and second MGs 1816 a, 1816 b comprise doped polysilicon, however, in other embodiments the SGs and MGs can be made otherconductive materials such as metal, for example. A charge-trapping layer1818 a is arranged between neighboring sidewalls of the first SG 1814 aand first MG 1816 a and extends under the first MG 1816 a. Similarly,charge trapping layer 1818 b and is arranged between neighboringsidewalls of the second SG 1814 b and second MG 1816 b and extends underthe second MG 1816 b. First and second dielectric sidewall spacers 1820a, 1820 b abut outermost side walls of the first and second MGs 1816 a,1816 b.

A CESL (contact etch-stop layer) 1822 conformally extends along inneropposing sidewalls of the SGs 1814 a, 1814 b, and also conformallyextends along outermost sidewalls of the first and second sidewallspacers 1820 a, 1820 b. The CESL 1822 can also extend over top surfacesof the first and second MG structures 1816 a, 1816 b and over the topsurface of the semiconductor body on either side of the gate structures.An interlayer dielectric (ILD) layer 1824 resides above the CESL layer1822.

As will be appreciated in greater detail below, first and secondsilicide-blocking caps 1826 a, 1826 b cover the upper surfaces of thefirst and second select gate structures 1814 a, 1814 b. The first andsecond silicide-blocking caps 1826 a, 1826 b prevent formation ofsilicides on the upper surfaces of the first and second SGs 1814 a, 1814b to limit or prevent metal ion contamination during a CMP processassociated with a replacement metal gate process of a HKMG process usedfor peripheral circuitry of the flash memory cell. In some embodiments,the first and second SGs 1814 a, 1814 b have respective top surfaceswith first and second indentations, respectively, and the first andsecond silicide-blocking caps 1826 a, 1826 b are arranged in the firstand second indentations, respectively.

In some embodiments, the first and second silicide-blocking caps 1826 a,1826 b can be formed of the same material as the ILD layer 1824, howeverin other embodiments the silicide-blocking caps 1826 a, 1826 b can bemade of a different material from the ILD layer 1824. For example, insome embodiments the ILD layer 1824 and the silicide-blocking caps 1826can both be made out of silicon dioxide (SiO2), however, in otherembodiments the silicide blocking caps 1826 can be made of SiO2 and theILD layer 1824 can be made of a low-K dielectric material.

During operation, the first and second memory cells 1802 a, 1802 b caneach be thought of as two transistors in series. Within each cell, onetransistor is the memory gate transistor (e.g., corresponding to MG 1816a), and the other is the select gate transistor (e.g. corresponding toSG 1814 a) which is controlled by a word line. Programming is performedby means of source-side channel hot-electron injection. Poly-to-polyFowler-Nordheim (FN) electron tunneling is employed for erasing. Tochange the cell value to a “0”, a negative electrical potential isapplied to both the MG and SG transistors, such that the electronsstored in the charge-trapping layer (e.g., 1818 a) are drained to thesource side of the memory cell (e.g., 1806 a or 1806 b). The electronsin the cells of a chip can be returned to normal “1” by the applicationof a strong positive electric field. Because the electrons tend toremain in the charge-trapping layer even when power is disconnected fromthe chip, the flash memory cells are said to be “non-volatile.”

FIG. 19 shows a flow diagram of a method 1900 according to someembodiments of the present disclosure. While disclosed method 1900 (andother methods described herein) is illustrated and described below as aseries of acts or events, it will be appreciated that the illustratedordering of such acts or events are not to be interpreted in a limitingsense. For example, some acts may occur in different orders and/orconcurrently with other acts or events apart from those illustratedand/or described herein. In addition, not all illustrated acts may berequired to implement one or more aspects or embodiments of thedescription herein. Further, one or more of the acts depicted herein maybe carried out in one or more separate acts and/or phases.

At 1902, a sacrificial spacer, which includes sidewalls and a topsurface, is formed over a semiconductor substrate.

At 1904, a first layer of conductive material is formed over the topsurface and sidewalls of the sacrificial spacer.

In 1906, a first etch back process is performed on the first layer ofconductive material to expose the top surface and upper sidewall regionsof the sacrificial spacer. A portion of the first layer of conductivematerial is typically left to cover lower sidewall regions of thesacrificial spacer.

In 1908, a conformal silicide-blocking layer is formed. This conformalsilicide-blocking layer extends over the etched back first layer ofconductive material. The conformal silicide-blocking layer also extendsover the top surface of the sacrificial spacer.

In 1910, a second etch back process is performed to remove the conformalsilicide-blocking layer from over the top surface of the sacrificialspacer while leaving a portion of the first conductive material, whichcorresponds to first and second select gate structures, along first andsecond lower sidewalls of the sacrificial spacer. The second etch backprocess also leaves first and second silicide-blocking caps over thefirst and second select gate structures, respectively.

In 1912, the sacrificial spacer is removed to form a recess betweenopposing sidewalls of the first and second select gate structures.

In 1914, an inter-layer dielectric (ILD) layer is formed. This ILD layerextends over the first and second silicide-blocking caps and extendsdownwardly into the recess.

In 1916, a chemical mechanical polishing (CMP) operation is performed onthe ILD layer to expose at least a portion of the first and secondsilicide-blocking caps.

In 1918, a silicide layer is formed on the semiconductor substrate inthe recess region while the silicide-blocking caps are exposed. Theexposed silicide-blocking caps prevent formation of silicide on thefirst and second select gate structures, while at the same time thesilicide layer is formed over source/drain regions of the structure.

FIGS. 20-34 show a series of cross-sectional views at various stages offorming a split gate memory cell according to some embodiments of thepresent disclosure. It will be appreciated that although thesecross-sectional views illustrate only a pair of split-gate memory cells,in typical embodiments an integrated circuit will include thousands,millions, billions, or even greater numbers of such split gate memorycells arranged in a memory array. The final integrated circuit alsoincludes peripheral circuitry that can utilize different process layers(e.g., HKMG and/or replacement metal gate technology), such as are usedin CMOS processes. Integration of the split-gate memory cells and theperipheral circuitry has caused a number of integration and reliabilityissues, which are mitigated in the process flow set forth below.

FIG. 20 illustrates a cross-sectional view of a semiconductor body 2100at one of the stages of forming split gate memory cells according tosome embodiments of the present disclosure. The semiconductor body 2100includes a semiconductor substrate 2102 on which memory devices andperipheral devices (e.g., CMOS devices) are formed. In some embodiments,the semiconductor substrate 2102 can be a bulk silicon substrate, asilicon on insulator (SOI) substrate, a binary semiconductor substrate(e.g., GaAs), tertiary semiconductor substrate (e.g., AlGaAs), or higherorder semiconductor substrate, for example. Any of these substrates caninclude doped regions formed in the substrate, one or more insulatinglayers formed in or on the substrate, and/or conducting layers formed inor on the substrate.

The illustrated semiconductor substrate 2102 has source/drain regions2104 that are formed, for example, by ion implantation or out-diffusionof dopants. A base dielectric layer 2106, such as an oxide layer or ahigh-k gate dielectric, resides on top of the semiconductor substrate2102 and can help protect the semiconductor body during future etchingsteps. Over the base dielectric layer 2106, a layer of sacrificialspacer material 2108 is formed. In some embodiments, the sacrificialspacer material comprises SiN, SiC and/or SiO2. A mask 2110, such as alayer of patterned photoresist for example, is formed on top of thesacrificial spacer material 2108.

FIG. 21 illustrates a cross-sectional view of a semiconductor body 2200,after the sacrificial spacer material 2108 has been patterned with themask 2110 in place to form a sacrificial spacer 2108′ having sidewallsand top surface. In some embodiments the sacrificial spacer 2108′ may beformed by carrying out either a plasma or reactive ion etch (RIE) or aselective wet etch while the mask 2110 is in place. A source/drainregion 2104 b, which covered by the patterned sacrificial spacer, is acommon or shared source/drain region, while other source/drain regions2104 a, 2104 c, which are left uncovered by the patterned sacrificialspacer, can correspond uniquely to a different split gate memory cells.After the sacrificial spacer 2108′ is patterned, the mask 2110 can beremoved.

FIG. 22 illustrates a cross-sectional view of a semiconductor body 2300,after forming a first layer of conductive material 2112 over the basedielectric 2106 as well as over the sacrificial spacer 2108. As will beappreciated further herein, this first layer of conductive material 2112will later correspond to select gate structures, and can be made ofdoped polysilicon in some embodiments. In other embodiments, the firstlayer of conductive material 2112 can be a metal layer.

FIG. 23 illustrates a cross-sectional view of a semiconductor body 2400,after depositing an etch protection layer 2114 on regions of thesubstrate not covered by the patterned sacrificial spacer 2108′. Thus,the etch protection layer 2114 can be formed on either side of thesacrificial spacer 2108′ to protect covered regions of the firstconductive layer 2112 from an upcoming etch-back process. In someembodiments, the etch protection layer 2114 comprises a BARC (bottomanti-reflective coating) material.

FIG. 24 illustrates a cross-sectional view of after performing a firstetch-back process on the first layer of conductive material 2112. Thefirst etch-back process removes portions of the first conductive layer2112 to expose the top surface 2108 a and upper sidewall regions 2108 b,2108 c of the sacrificial spacer. Thus, the first etch-back processleaves portions 2112 a, 2112 b of the first conductive layer coveringlower sidewall regions of the sacrificial spacer 2108′. After etching,height of the first conductive layer can be reduced to approximatelyhalf of a height level of the sacrificial spacer 2108′. In someembodiments, the remaining portion of the first conductive layer has topsurfaces 2115 that have a curved geometry with an indention in a centralregion thereof. The etch protection layer 2114 protects the first layerof conductive material over the source/drain regions and is removedafter the first etch-back process.

FIG. 25 illustrates a cross-sectional view after a conformalsilicide-blocking layer 2116 has been formed. The silicide-blockinglayer 2116 extends over the top surfaces 2115 of the remaining portionof the first layer of conductive material, and also extends over the topsurface 2108 a and upper sidewall regions 2108 b, 2108 c of thesacrificial spacer 2108′. In some embodiments, the silicide-blockinglayer 2116 comprises SiO2 (silicon dioxide).

FIG. 26 illustrates a cross-sectional view of a semiconductor body 2700,after a second etch back procedure has been performed. This second etchback procedure etches away the portions of the first conductive layer2112 over the source/drain regions; and also removes thesilicide-blocking layer from over the top surface of the sacrificialspacer. Thus, the second etch back process results in first and secondsilicide-blocking caps 2116 a, 2116 b that are arranged over first andsecond select gates 2112 c, 2112 d. In some embodiments, the second etchback process comprises a wet etch, but could also be a dry etch, such asa plasma etch or RIE procedure.

FIG. 27 illustrates a cross-sectional view of a semiconductor body 2800,after forming a charge-trapping layer 2118, a second conductive materiallayer 2120 and a dielectric spacer layer 2122 over the entiresemiconductor body 2102. In some embodiments, the second conductivelayer 2120 comprises poly silicon and the dielectric spacer layer 2122comprises SiO2.

FIG. 28 a illustrates a cross sectional view of an embodiment ofcharge-trapping layer 2118. In this example, charge-trapping layer 2118a comprises a first oxide layer 2119 a, a nitride layer 2119 b, and asecond oxide layer 2119 c. During operation of the memory cell, thefirst and/or second oxide layers 2119 a, 2119 c are structured topromote electron tunneling to and from the nitride layer 2119 b, suchthat the nitride layer 2119 b can retain trapped electrons that alterthe threshold voltage of the cell in a manner that corresponds to a datastate stored in the cell.

FIG. 28 b illustrates a cross sectional view of an alternate embodimentof charge-trapping layer 2118. In this example, charge-trapping layer2118 b comprises a first oxide layer 2119 d, a layer of silicon dots2119 e, and a second oxide layer 2119 f. During operation of the memorycell, the first and/or second oxide layers 2119 d, 2119 f are structuredto promote electron tunneling to and from the layer of silicon dots 2119e, such that charge can become trapped on the silicon dots and alter thethreshold voltage of the cell in a manner that corresponds to a datastate stored in the cell. In some embodiments, the Si dots havediameters ranging from approximately 5 nm to approximately 20 nm.

FIG. 29 illustrates a cross sectional view of a semiconductor body 2900,after etching parts of the oxide layer 2122 and the second conductivelayer 2120 to form a pair of MGs 2120 a, 2120 b on either side of thesacrificial spacer 2108 adjacent the outer side walls of SGs 2112 c and2112 d. Dielectric sidewall spacers 2122 a, 2122 b are also formed,being made out of oxide, for example. The MGs 2120 a, 2120 b extendunder the dielectric spacers 2122 a, 2122 b. In some embodiments, thesecond conductive layer 2120 and the dielectric spacer layer 2122 areetched off using wet etching.

FIG. 30 illustrates a cross sectional view of a semiconductor body 3000,after removing exposed parts of the charge-trapping layer 2118 and thesacrificial spacer 2108 to form a recess 2121. This etching exposes thebase dielectric layer 2106 in regions where there are no SGs or MGs. Insome embodiments, the charge-trapping layer 2118 and the sacrificialspacer 2108 are removed using a wet etchant combination of HF+H3PO4.

FIG. 31 illustrates a cross sectional view of a semiconductor body 3100,after etching away exposed regions of the base dielectric layer 2106,forming a salicide 2124 on upper regions of the source/drain regions,performing an etch-back process on the top surfaces of the MGs 2120 aand 2120 b, while a BARC layer (not shown) overlies the salicide layer2124 and protects the rest of the semiconductor body, and forming a CESLlayer 2126 encapsulating the gate structures and the base of thesemiconductor body 2102. In some embodiments, the salicide layer 2124comprises NiSi and the CESL layer comprises SiN and the dielectricsidewall spacers 2122 a and 2122 b comprise a nitride. The etch backprocess performed on the MGs gives a non-planar/curved geometry fortheir top surfaces and makes sure the MG poly layer is protected withthe CESL layer from future polishing steps.

FIG. 32 illustrates a cross sectional view of a semiconductor body 3200,after depositing an ILD layer 2128 entirely over the semiconductor body.In some embodiments, the ILD layer 2128 comprises SiO2 or TEOS(tetetraethylorthosilicate), but the ILD layer can also be a low-kdielectric with a dielectric constant of less than about 2.8.

FIG. 33 illustrates a cross sectional view of a semiconductor body 3300,after performing a CMP (chemical mechanical polishing) on the ILD layer2128. This CMP process polishes until a height level of the CESL layeron top of the MG is reached, and thus reduces height of the SGstructures (SG with protective dielectric on top) to that level.Semiconductor body 3300 has a planar top surface that exposes part ofthe silicide-blocking layer over the SGs (2116 a and 2116 b), part ofthe CESL layer 2126 over the MGs and portions of charge-trapping layer2118 in between the SGs and the MGs at that height level.

FIG. 34 illustrates a cross sectional view of a semiconductor body 3400,after forming metal contacts 2130 a-2130 c. Metal contacts 2130 a-2130 cextend downward to the silicides on upper portion of source/drain (S/D)regions 2104, and can comprise Ti/TiN as a buffer layer which is filledwith W in some embodiments.

It will be appreciated that while reference is made throughout thisdocument to exemplary structures in discussing aspects of methodologiesdescribed herein that those methodologies are not to be limited by thecorresponding structures presented. Rather, the methodologies (andstructures) are to be considered independent of one another and able tostand alone and be practiced without regard to any of the particularaspects depicted in the Figs. Additionally, layers described herein, canbe formed in any suitable manner, such as with spin on, sputtering,growth and/or deposition techniques, etc.

Also, equivalent alterations and/or modifications may occur to thoseskilled in the art based upon a reading and/or understanding of thespecification and annexed drawings. The disclosure herein includes allsuch modifications and alterations and is generally not intended to belimited thereby. For example, although the figures provided herein, areillustrated and described to have a particular doping type, it will beappreciated that alternative doping types may be utilized as will beappreciated by one of ordinary skill in the art.

The present disclosure relates to a structure and method for formingself-aligned split gate flash memory cells that can be embedded with aN28 (28 nm) technology or beyond. The self-aligned flash memory formedaround the sacrificial spacer provides precise control of the SG and MGcritical dimension and thus improves shrink capability. The top surfacesof the SG and MG of each flash memory cell has a curved geometry whichwhen filled with dielectrics, provides protection during salicideformation. The absence of salicide prevents metal ion contaminationduring the CMP process associated with HKMG integrated circuit. Thus,the method is also compatible with RMG process.

In some embodiments, the present disclosure relates to a method offorming a split gate memory cell over a semiconductor substrate. In thismethod, a sacrificial spacer is formed over a semiconductor substrate. Afirst layer of conductive material is formed over a top surface andsidewalls of the sacrificial spacer. A first etch back process is formedon the first layer of conductive material to expose the top surface ofthe sacrificial spacer and upper sidewall regions of the sacrificialspacer. A conformal silicide-blocking layer is then formed which extendsover the etched back first layer of conductive material and over the topsurface of the sacrificial spacer.

In other embodiments, a split gate memory device is disposed over asemiconductor substrate. The devices includes a common source/drainregion disposed in the semiconductor substrate, and first and secondselect gate structures arranged on opposite sides of the common sourcedrain. First and second silicide-blocking caps are arranged on uppersurfaces of the first and second select gate structures, respectively.

Still other embodiments relate to a split gate memory device disposedover a semiconductor substrate. The split gate memory device includes afirst memory gate (MG) and a first select gate (SG). The first SG have atop surface covered by a first silicide-blocking cap. A first dielectricspacer abuts a first portion of an outer sidewall of the first MG. Thefirst MG extends under the first dielectric spacer. A firstcharge-trapping layer is arranged between neighboring sidewalls of thefirst MG and the first SG. The first charge-trapping layer extends underthe first MG.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of forming a split gate memory cell overa semiconductor substrate comprising: forming a sacrificial spacer overa semiconductor substrate; forming a first layer of conductive materialover a top surface and sidewalls of the sacrificial spacer; performing afirst etch back process on the first layer of conductive material toexpose the top surface of the sacrificial spacer and upper sidewallregions of the sacrificial spacer; and forming a conformalsilicide-blocking layer that extends over the etched back first layer ofconductive material and over the top surface of the sacrificial spacer.2. The method of claim 1, further comprising: performing a second etchback process to remove the conformal silicide-blocking layer from overthe top surface of the sacrificial spacer while leaving a portion of thefirst conductive material, which corresponds to first and second selectgate structures, along first and second lower sidewalls of thesacrificial spacer and while leaving first and second silicide-blockingcaps over the first and second select gate structures, respectively. 3.The method of claim 2, further comprising: removing the sacrificialspacer to form a recess between inner sidewalls of the first and secondselect gate structures; forming an inter-layer dielectric (ILD) layerextending over the first and second silicide-blocking caps and extendingdownwardly into the recess; and performing a chemical mechanicalpolishing (CMP) operation on the ILD layer to expose at least a portionof the silicide-blocking layer.
 4. The method of claim 3, furthercomprising: forming a silicide layer on the semiconductor substrate inthe recess while the portion of the silicide-blocking layer is exposedto prevent formation of silicide on the first and second select gatestructures.
 5. The method of claim 4, wherein the silicide-blockinglayer comprises SiO₂.
 6. The method of claim 3, further comprising:prior to removing the sacrificial spacer, forming a conformalcharge-trapping layer extending over the top surface of the sacrificialspacer and over the first and second silicide-blocking caps; forming aconformal second conductive layer over the charge-trapping layer;forming a conformal dielectric spacer layer over the second conductivelayer; and performing a third etch back procedure to remove portions ofthe conformal charge trapping layer, portions of the conformal secondconductive layer, and portions of the conformal spacer dielectric layer,to form first and second self-aligned memory gate structures onoutermost sidewalls of the first and second select gate structures,respectively.
 7. The method of claim 3, further comprising: forming acommon source/drain region in the substrate, wherein the first andsecond select gate structures are arranged on opposite sides of thecommon source/drain region; and forming metal contacts extending throughthe ILD to the common source/drain region.
 8. The method of claim 7,wherein the metal contacts comprise Ti/TiN (titanium/titanium nitride)or W (tungsten).
 9. The method of claim 7, further comprising: forming asilicide layer on directly on an upper region of the common source/drainregion while the portion of the silicide-blocking layer is exposed toprevent formation of silicide on the first and second select gatestructures.
 10. The method of claim 2: wherein the first and secondselect gate structures have first and second top surfaces, respectively,having respective first and second indentations in central regionsthereof; and wherein the first and second silicide-blocking caps arearranged in the first and second indentations, respectively.
 11. A splitgate memory device disposed over a semiconductor substrate comprising: acommon source/drain region disposed in the semiconductor substrate;first and second select gate structures arranged on opposite sides ofthe common source drain; and first and second silicide-blocking caps onupper surfaces of the first and second select gate structures,respectively.
 12. The split gate memory device of claim 11, wherein thefirst and second select gates have respective first and second topsurfaces with first and second indentations, respectively, and whereinthe first and second silicide blocking caps are arranged in the firstand second indentations, respectively.
 13. The split gate memory deviceof claim 11, further comprising: a base oxide layer separating lowersurfaces of the first and second select gate structures from an uppersurface the semiconductor substrate; first and second memory gatesarranged about outermost sidewalls of the first and second select gatestructures, respectively; and first and second sidewall spacers abuttingoutermost sidewalls the first and second memory gates, respectively,wherein the first memory and second memory gates extend under the firstand second sidewall spacers.
 14. The split gate memory device of claim13, further comprising: a silicide layer extending over a base surfaceof the semiconductor substrate on either side of the first and secondselect gate structures; and a contact etch stop layer (CESL) coveringinner sidewalls of the first and second select gates and covering outersidewalls of the first and second memory gates, wherein the CESL coversupper surfaces of the first and second memory gates and covers uppersurfaces of the first and second sidewall spacers.
 15. The split gatememory device of claim 13, further comprising: a charge-trapping layerarranged between neighboring sidewalls of the first memory gate and thefirst select gate and extending under the first memory gate.
 16. Thesplit gate memory device of claim 15, wherein the charge-trapping layercomprises and oxide-nitride-oxide (ONO) charge trapping layer.
 17. Thesplit gate memory device of claim 15, wherein the charge-trapping layercomprises: a first dielectric layer; a layer of sphere-like silicon dotsarranged over a surface of the first dielectric layer; and a seconddielectric layer arranged over the layer of sphere-like silicon dots.18. A split gate memory device disposed over a semiconductor substratecomprising: a first memory gate (MG) and a first select gate (SG), thefirst SG having a top surface covered by a first silicide-blocking cap;a first dielectric spacer abutting a first portion of an outer sidewallof the first MG, wherein the first MG extends under the first dielectricspacer; and a first charge-trapping layer arranged between neighboringsidewalls of the first MG and the first SG, the first charge-trappinglayer extending under the first MG.
 19. The split gate memory device ofclaim 18, a second memory gate (MG) and a second select gate (SG), thesecond SG having a top surface covered by a second silicide-blockingcap; a second dielectric spacer abutting an outer sidewall of the secondMG, wherein the second MG extends under the second dielectric spacer;and a second charge-trapping layer arranged between neighboringsidewalls of the second MG and the second SG, the second charge-trappinglayer extending under the second MG.
 20. The split gate memory device ofclaim 19, further comprising: a common or shared source/drain regionarranged between the first and second select gates and having a silicideon an upper region thereof.